HY5PS1G821M Datasheet, PDF (64/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
5.3 Output Buffer Levels
5.3.1 Output AC Test Conditions
Symbol
V_OH
V_OL
V_OTR
Parameter
Minimum Required Output Pull-up under AC Test Load
Maximum Required Output Pull-down under AC Test Load
Output Timing Measurement Reference Level
1. The VDDQ of the device under test is referenced.
SSTL_18 Class II
V_TT + 0.603
V_TT - 0.603
0.5 * V_DDQ
Units
V
V
V
Notes
1
5.3.2 Output DC Current Drive
Symbol
Parameter
SSTl_18 Class II
Units
Notes
I_OH(dc) Output Minimum Source DC Current
- 13.4
mA
1, 3, 4
I_OL(dc) Output Minimum Sink DC Current
13.4
mA
2, 3, 4
1. V_DDQ = 1.7 V; V_OUT = 1420 mV. (V_OUT - V_DDQ)/I_OH must be less than 21 ohm for values of V_OUT between V_DDQ and V_DDQ - 280
mV.
2. V_DDQ = 1.7 V; V_OUT = 280 mV. V_OUT/I_OL must be less than 21 ohm for values of V_OUT between 0 V and 280 mV.
3. The dc value of V_REF applied to the receiving device is set to V_TT
4. The values of I_OH(dc) and I_OL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current
capability to ensure V_IH min plus a noise margin and V_IL max minus a noise margin are delivered to an SSTL_18 receiver. The
actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define
a convenient driver current for measurement.
5.3.3 OCD defalut characteristics
Description
Output impedance
Pull-up and pull-
down mismatch
Output slew rate
Parameter
Sout
Min
12.6
0
1.5
Nom
18
-
Max
23.4
4
5
Unit Notes
ohms 1,2
ohms 1,2,3
V/ns 1,4,5,6,7
Note 1: Absolute Specifications (0°C ≤ T_CASE ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
Note 2: Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.
Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol
must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
Note 3: Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and
voltage.
Note 4: Slew rate measured from vil(ac) to vih(ac).
Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew
rate as measured from AC to AC. This is guaranteed by design and characterization.
Note 6: DRAM output slew rate specification Table.
Note 7: DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins.
Rev. 0.2 / Oct. 2005
64