HY5PS1G821M Datasheet, PDF (74/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
Parameter
Exit active power down to read
command
Exit active power down to read
command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
Average periodic Refresh
Interval
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down
mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down
mode)
ODT to power down entry
latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains
ON after CKE asynchronously
drops LOW
Symbol
tXARD
DDR2-400 3-3-3
min
max
2
DDR2-533 4-4-4
Unit
min
max
2
tCK
tXARDS
6 - AL
6 - AL
tCK
t_CKE
3
3
tCK
tREFI
t_AOND
t_AON
t_AONPD
t_AOFD
t_AOF
t_AOFPD
tANPD
tAXPD
tOIT
tDelay
7.8
7.8
us
2
2
2
2
tCK
tAC(min)
tAC(max)+1 tAC(min)
tAC(max)+
1
ns
tAC(min)+2
2tCK+tAC
(max)+1
tAC(min)+2
2tCK+tAC
(max)+1
ns
2.5
2.5
2.5
2.5
tCK
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)+
0.6
ns
tAC(min)+2
2.5tCK+tAC
(max)+1
tAC(min)+2
2.5tCK+tA
C(max)+1
ns
3
3
tCK
8
8
tCK
0
12
0
12
ns
tIS+tCK+tIH
tIS+tCK+tI
H
ns
Note
1
1, 2
16
17
15
* : tRAS(min) , tRC(min) specification for DDR2-400 4-4-4 is 45ns, 60ns respectively.
Rev. 0.2 / Oct. 2005
74