HY5PS1G821M Datasheet, PDF (41/79 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM(DDP)

1HY5PS12421(L)M
HY5PS12821(L)M
Example 5: Burst Read Operation Followed by Precharge:
RL = 4, AL = 0, CL = 4, BL = 8, t_RTP > 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD ^{Post CAS}
READ A
NOP
NOP
NOP
AL + 2 Clks + max{tRTP;2 tCK}*
NOP
Precharge A
NOP
NOP
Bank A
Activate
DQS/DQS
AL = 0
DQ’s
CL =4
RL = 4
first 4-bit prefetch
> = t_RP
> = t_RAS
DOUT A₀ DOUT A₁ DOUT A₂ DOUT A₃ DOUT A₄ DOUT A₅ DOUT A₆ DOUT A₇
> = t_RTP
second 4-bit prefetch
* : rounded to next interger
Rev. 0.2 / Oct. 2005
41