MC68HC705E5 Datasheet, PDF (93/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Motorola Bus (M Bus) Interface
Operation During Wait Mode
MAL = 1 and MSTA = 0. If one master attempts to start transmission
while the bus is being engaged by another master:
1. The hardware will inhibit the transmission.
2. The MSTA bit will switch from one to zero without generating a
stop condition.
3. Interrupt to CPU will be generated.
4. MAL will be set to indicate that the attempt to engage the bus has
failed.
In consideration of these cases, the slave service routine should test the
MAL first, and software should clear the MAL bit if it is set.
11.9 Operation During Wait Mode
During wait mode the M-bus block is idle. If in slave mode, the M-bus
block will wake up on receiving a valid start condition. If the interrupt is
enabled, the CPU will come out of wait mode after the end of a byte
transmission.
11.10 Operation During Stop Mode
In stop mode, the whole block is disabled.
MC68HC705E5 — Rev. 1.0
General Release Specification
Motorola Bus (M Bus) Interface
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