MC68HC705E5 Datasheet, PDF (92/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Motorola Bus (M Bus) Interface
11.8.5 Generation of a Repeated Start Signal
If at the end of data transfer the master still wants to communicate on the
bus, it can generate another start signal followed by another slave
address without first generating a stop signal. A program example is
shown here.
RESTART BCLR
BSET
LDA
STA
5,MCR
5,MCR
#CALLING
MDR
; ANOTHER START (RESTART) IS
; GENERATED BY THESE TWO
; CONSEQUENCE INSTRUCTION
; GET THE CALLING ADDRESS
; TRANSMIT THE CALLING
; ADDRESS
11.8.6 Slave Mode
In the slave service routine, the master addressed as slave bit (MAAS)
should be tested to see if a calling of its own address has just been
received. If MAAS is set, software should set the transmit/receive mode
select bit (MTX bit of MCR) according to the R/W command bit (SRW).
Writing to the MCR clears the MAAS automatically. A data transfer may
then be initiated by writing information to MDR or dummy reading from
MDR.
In the slave transmitter routine, the received acknowledge bit (RXAK)
must be tested before transmitting the next byte of data. If RXAK is set,
indicating an end of the data signal from the master receiver, then RXAK
must switch from transmitter mode to receiver mode by software. A
dummy read must follow to release the SCL line so that the master can
generate a stop signal.
11.8.7 Arbitration Lost
If more than one master wants to engage the bus simultaneously, only
one master wins and the others lose arbitration. The arbitration loss
devices immediately switch to slave receive mode by hardware. Their
data output to the SDA line is stopped, but the internal transmitting clock
still runs until the end of the current byte transmission. An interrupt
occurs when this dummy byte transmission is accomplished with
General Release Specification
Motorola Bus (M Bus) Interface
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MC68HC705E5 — Rev. 1.0