MC68HC705E5 Datasheet, PDF (63/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Phase-Locked Loop (PLL) Synthesis
Phase-Locked Loop Control Register
9.3 Phase-Locked Loop Control Register
This read/write register contains the control bits which select the PLL
frequency and enable/disable the synthesizer.
Address: $0007
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
BCS
0
BWC PLLON VCOTST PS1
PS0
Write:
Reset: 0
0
0
0
1
1
0
1
Figure 9-2. Phase-Locked Loop Control Register (PLLCR)
BCS — Bus Clock Select
When this bit is set, the output of the PLL is used to generate the
internal processor clock. When clear, the internal bus clock is driven
by the crystal (OSC1 ÷ 2). Once BCS has been changed, it may take
up to 1.5 OSC1 cycles + 1.5 PLLOUT cycles to make the transition.
During the transition, the clock select output will be held low and all
CPU and timer activity will cease until the transition is complete.
Before setting BCS, allow at least a time of t_PLLS after PLLON is set.
This bit cannot be set unless the PLLON bit is already set on a
previous instruction. Reset clears this bit.
BWC — Bandwidth Control
This bit selects high bandwidth control when set and low bandwidth
control when clear. The low bandwidth driver is always enabled, so
this bit determines whether the high bandwidth driver is on or off.
When the PLL is turned on, the BWC bit should be set to a logic 1 for
a time of 90% t_PLLS to allow the PLL time to acquire a frequency close
to the desired frequency. The BWC bit should then be cleared and
software should delay for a time 10% t_PLLS to allow the PLL time to
make the final adjustments. The PLL clock cannot be used (BCS bit
set). Although it is NOT prohibited in hardware, the BCS bit should not
be set unless the BWC bit is cleared and the proper delay times have
been followed. The PLL will generate a lower jitter clock when the
BWC bit is cleared. Reset clears this bit.
MC68HC705E5 — Rev. 1.0
General Release Specification
Phase-Locked Loop (PLL) Synthesis
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