MC68HC705E5 Datasheet, PDF (62/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Phase-Locked Loop (PLL) Synthesis
t_REF
OSC1
CRYSTAL
OSCILLATOR
0.1 µF
PHASE
DETECT
PCOMP
V_DDSYN
0.1 µF
XFC
OSC1
LOOP FILTER
PLLOUT
CLOCK
VCO
SELECT
BCS
÷2
TO CLOCK
GENERATION
CIRCUITRY
t_FB
FREQUENCY
DIVIDER
PS1 PS0
Figure 9-1. PLL Circuit
To change PLL frequencies, follow the procedure outlined here:
1. Clear BCS to enable the low-frequency bus rate.
2. Clear PLLON to disable the PLL and select high bandwidth.
3. Select the speed using PS1 and PS0.
4. Set PLLON to enable the PLL.
5. Wait a time of 90% t_PLLS for the PLL frequency to stabilize and
select manual low bandwidth, wait another 10% t_PLLS.
6. Set BCS to switch to the high-frequency bus rate
The user cannot switch among the high speeds with the BCS bit set.
Following the procedure above will prevent possible bursts of
high-frequency operation during the re-configuration of the PLL.
Whenever the PLL is first enabled, the wide bandwidth mode should be
used. This enables the PLL frequency to ramp up quickly. When the
output frequency is near the desired frequency, the filter is switched to
the narrow bandwidth mode to make the final frequency more stable.
General Release Specification
Phase-Locked Loop (PLL) Synthesis
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Go to: www.freescale.com
MC68HC705E5 — Rev. 1.0