MC68HC705E5 Datasheet, PDF (20/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Description
1.4 Mask Options
The M68HC705E5 has these four mask options which are handled with
five EPROM bits (MOR).
1. STOP instruction (enable/disable)
2. IRQ (edge-sensitive only or edge- and level-sensitive)
3. COP watchdog timer (enable/disable)
4. CPI Rate (1 second, 0.5 second, or 0.25 second)
ROM versions of this device will have these options programmed by the
factory. Refer to 13.5 Mask Option Register for additional information.
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active low.
1.5 Functional Pin Description
Figure 1-2 shows the single-chip mode pinout for the MC68HC705E5.
Refer to the following subsections for a description of the pins.
IRQ 1
RESET 2
OSC1 3
OSC2 4
PB7/SCL 5
PB6/SDA 6
PB5/SDIO 7
PB4/SCK 8
PB3/TIPL 9
PB2 10
PB1 11
PB0 12
V_DD
13
V_SS
14
28 XFC
27
V_DDSYN
26 ^PA0
25 PA1
24 PA2
23 PA3
22 PA4
21 PA5
20 PA6
19 PA7
18 PC0
17 PC1
16 PC2
15 PC3
Figure 1-2. Single-Chip Mode Pinout
General Release Specification
General Description
For More Information On This Product,
Go to: www.freescale.com
MC68HC705E5 — Rev. 1.0