MC68HC705E5 Datasheet, PDF (57/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Timer
Timer Control and Status Register
8.3 Timer Control and Status Register
The timer control and status register (TCSR) contains the timer interrupt
flag, the timer interrupt enable bits, and the real-time interrupt rate select
bits. Figure 8-2 shows the value of each bit in the TCSR when coming
out of reset.
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOF
RTIF TOFE RTIE TOFA RTIFA
RT1
RT0
Write:
Reset: 0
0
0
0
0
0
1
1
Figure 8-2. Timer Control and Status Register (TCSR)
TOF — Timer Over Flow
TOF is a clearable, read-only status bit and is set when the 8-bit ripple
counter rolls over from $FF to $00. A CPU interrupt request will be
generated if TOFE is set. Clearing the TOF is done by writing a logic 1
to TOFA. This is a read-only bit. Reset also clears TOF.
RTIF — Real-Time Interrupt Flag
The real-time interrupt circuit consists of a 3-stage divider and a
one-of-four selector. The clock frequency that drives the RTI circuit is
f_op/2¹³ (or f_op/8192) with three additional divider stages giving a
maximum interrupt period of four seconds at a crystal frequency of
32.768 kHz. RTIF is a clearable, read-only status bit and is set when
the output of the chosen (one-of-four selection) stage goes active. A
CPU interrupt request will be generated if RTIE is set. Clearing the
RTIF is done by writing a logic 1 to RTIFA. Reset also clears RTIF.
TOFE — Timer Overflow Enable
When this bit is set, a CPU interrupt request is generated when the
TOF bit is set. Reset clears this bit.
MC68HC705E5 — Rev. 1.0
General Release Specification
Timer
For More Information On This Product,
Go to: www.freescale.com