MC68HC705E5 Datasheet, PDF (78/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Motorola Bus (M Bus) Interface
11.6 M-Bus Registers
Five different registers are used in the M-bus interface. The internal
configuration of these registers is discussed in the following paragraphs.
NOTE:
The register addresses show only the low-order address bits (for
example ABL3–ABL0). The registers can be placed anywhere in the
device memory map by generating an appropriate module select signal
in the map logic.
A block diagram of the M-bus system is shown in Figure 11-3.
11.6.1 M-Bus Address Register
Address: $0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MAD7
Write:
MAD6
MAD5
MAD4
MAD3
MAD2
MAD1
Reset: 0
0
0
0
0
0
0
—
= Unimplemented
Figure 11-3. M-Bus Address Register (MADR)
Bit 1–Bit 7
Each of these bits contains its own specific slave address. This
register is cleared upon reset.
General Release Specification
Motorola Bus (M Bus) Interface
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MC68HC705E5 — Rev. 1.0