MC68HC705E5 Datasheet, PDF (70/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Computer Operating Properly (COP) Watchdog
10.4 COP During Wait Mode
The CPU clock halts during wait mode, but the oscillator and the COP
system are still active. The software should exit wait mode to service the
COP system before the COP timeout period.
10.5 COP During Stop Mode
Prior to entry into stop mode, the COP should be cleared. This allows for
proper stop recovery and eliminates a possible COP time-out during
stop mode recovery, if the COP was about to time out prior to the STOP
instruction. If enabled, stop mode turns off the oscillator and, therefore,
will stop the COP.
General Release Specification
Computer Operating Properly (COP) Watchdog
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MC68HC705E5 — Rev. 1.0