MC68HC705E5 Datasheet, PDF (67/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification — MC68HC705E5
Section 10. Computer Operating Properly (COP)
Watchdog
10.1 Contents
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
10.3 System Control and Status Register. . . . . . . . . . . . . . . . . . . . .68
10.4 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
10.5 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
10.2 Introduction
The COP watchdog system is a mask-programmable feature which will
generate a system reset if not serviced within the specified COP timeout
period. The COP counter chain is derived from an output of the CPI
circuit. This input signal is divided to give the COP reset rate selected by
the first write to the system control and status register (SCSR) located at
address $13.
A COP reset is done by writing a logic 0 to bit zero of address $1FF0.
This will reset the COP counter chain and begin the timeout countdown
again. The COP counter chain is also cleared when the MCU is in reset
or stop mode.
MC68HC705E5 — Rev. 1.0
General Release Specification
Computer Operating Properly (COP) Watchdog
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