MC68HC705E5 Datasheet, PDF (82/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Motorola Bus (M Bus) Interface
11.6.3 M-Bus Control Register
The M-bus control register (MCR) provides five control bits and is
cleared upon reset.
Address: $001A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MEN MIEN MSTA MTX TXAK MMUX
Write:
Reset: 0
0
0
0
0
0
—
—
= Unimplemented
Figure 11-6. M-Bus Control Register (MCR)
MEN — M-Bus Enable Bit
If MEN is set, the M-bus interface system is enabled. If MEN is
cleared, the interface is reset and disabled. The MEN bit must be set
first before any bits of MCR are set.
MIEN — M-Bus Interrupt Enable Bit
If MIEN is set, an interrupt occurs provided the MIF flag in the status
register is set and the I bit in the condition code register is cleared. If
MIEN is cleared, the M-bus interrupt is disabled.
MSTA — Master/Slave Mode Select Bit
Upon reset, this bit is cleared. When this bit is changed from a logic 0
to a logic 1, a start signal is generated on the bus, and master mode
is selected. When this bit is changed from a logic 1 to a logic 0, a stop
signal is generated and the operating mode changes from master to
slave.
In master mode, a bit clear immediately followed by a bit set
generates a repeated start signal (see Figure 11-1) without
generating a stop signal.
1 = Master
0 = Slave
General Release Specification
Motorola Bus (M Bus) Interface
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MC68HC705E5 — Rev. 1.0