MC68HC705E5 Datasheet, PDF (31/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Condition Code Register
3.5 Condition Code Register
The CCR is a 5-bit register in which the H, N, Z, and C bits are used to
indicate the results of the instruction just executed, and the I bit is used
to enable interrupts. These bits can be tested individually by a program,
and specific actions can be taken as a result of their state. Each bit is
explained in the following paragraphs.
Bit 4
3
2
1
Bit 0
H
I
N
Z
C
Figure 3-5. Condition Code Register (CCR)
Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
Interrupt (I)
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the I bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was zero.
Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit also is affected during bit test and branch instructions and during
shifts and rotates.
MC68HC705E5 — Rev. 1.0
General Release Specification
Central Processing Unit (CPU)
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