MC68HC705E5 Datasheet, PDF (34/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Interrupts
Freescale Semiconductor, Inc.
Unlike RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete. The current instruction is the one already fetched
and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the I-bit
state.
Table 4-1. Vector Address for Interrupts and Reset
Register
N/A
N/A
N/A
TCSR
N/A
CPICSR
SSR
MSR
Flag
Name
N/A
N/A
N/A
TOF
RTIF
CPIF
SF
MIF
Interrupts
Reset
Software
External Interrupt
Timer Overflow
Real-Time Interrupt
Custom Periodic Interrupt
Synchronous Serial Interrupt
M-Bus Interrupt
CPU
Interrupt
RESET
SWI
IRQ
TIMER
TIMER
CPI
SSI
M Bus
Vector
Address
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF8–$1FF9
$1FF6–$1FF7
$1FF4–$1FF5
$1FF2–$1FF3
General Release Specification
Interrupts
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MC68HC705E5 — Rev. 1.0