MC68HC705E5 Datasheet, PDF (80/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Motorola Bus (M Bus) Interface
11.6.2 M-Bus Frequency Divider Register
Address: $0019
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
FD4
FD3
FD2
FD1
FD0
Reset: —
—
—
0
0
0
0
0
= Unimplemented
Figure 11-5. M-Bus Frequency Divider Register (MFDR)
Bit 0–Bit 4
These bits are used for clock rate selection. The serial bit clock
frequency is equal to the CPU clock divided by the divider shown in
Table 11-1. This register is cleared upon reset.
For a 4-MHz external crystal operation (2-MHz internal operating
frequency), the serial bit clock frequency of the M-bus ranges from
460 Hz to 90,909 Hz.
General Release Specification
Motorola Bus (M Bus) Interface
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MC68HC705E5 — Rev. 1.0