MC68HC705E5 Datasheet, PDF (104/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Synchronous Serial Interface (SSI)
12.4.3 SSI Data Register
This register is located at address $000C and is both the transmit and
receive data register. This system is not double buffered but writes to
this register during transfers are masked and will not destroy the
previous contents. The SDR can be read at any time but if a transfer is
in progress the results may be ambiguous. This register should only be
written to when the SSI is enabled (SE = 1).
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Reset Results Unknown
Figure 12-6. SSI Data Register (SDR)
12.5 SSI During Stop Mode
In stop mode, the SSI halts operation. The SDIO and SCK pins will
maintain their states.
If the SSI was nearing completion of a transfer when stop mode is
entered, it might be possible for the SSI to generate an interrupt request
and cause the processor to immediately exit stop mode. To prevent this
occurrence, the programmer should ensure that all transfers are
complete before entering stop mode.
If the SSI is configured to slave mode, then further care should be taken
in entering stop mode. In slave mode, the SCK pin will still accept a clock
from an external master, allowing potentially unwanted transfers to take
place and power consumption to be increased. Note that the SSI will not
generate interrupt requests in this situation. However, on exiting stop
mode through some other means, the SF flag may be found to be set. If,
at this point, SIE is also set, an interrupt request will be generated.
NOTE: To avoid these potential problems, it is safer to disable the SSI
completely (SE = 0) before entering stop mode.
General Release Specification
Synchronous Serial Interface (SSI)
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MC68HC705E5 — Rev. 1.0