MC68HC705E5 Datasheet, PDF (40/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Interrupts
Freescale Semiconductor, Inc.
4.8 Synchronous Serial Interface Interrupt (SSI)
The SSI flag and enable bits are located in the SSI control (SCR) and
status (SSR) registers. An SSI interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
locations $1FF4 and $1FF5. For additional information, refer to 12.4 SSI
Registers.
4.9 M-Bus (I²C) Interrupt (M Bus)
The MIF flag and enable bits are located in the M-bus status (MSR) and
control (MCR) registers. An M-bus interrupt will vector to the interrupt
service routine located at the address specified by the contents of
memory locations $1FF2 and $1FF3. For further information, refer to
11.6 M-Bus Registers.
4.10 Operation During Stop Mode
The timer system is cleared and the CPI counter is halted when going
into stop mode. When stop mode is exited by an external interrupt or an
external RESET, the internal oscillator will resume, followed by a
4064-cycle internal processor oscillator stabilization delay. The timer
system counter is then cleared and operation resumes. The CPI will
continue counting once the oscillator resumes and does not wait for the
oscillator to stabilize.
4.11 Operation During Wait Mode
The CPU clock halts during wait mode, but the timer and CPI remain
active. A timer interrupt or custom periodic interrupt, SSI, and M bus will
cause the processor to exit wait mode if the interrupts are enabled.
General Release Specification
Interrupts
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MC68HC705E5 — Rev. 1.0