MC68HC705E5 Datasheet, PDF (35/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Interrupts
Hardware Controlled Interrupt Sequence
4.3 Hardware Controlled Interrupt Sequence
The following three functions (RESET, STOP, and WAIT) are not in the
strictest sense an interrupt; however, they are acted upon in a similar
manner. See Figure 4-1 and Figure 4-2. A discussion is provided below.
1. RESET — A low input on the RESET input pin causes the program
to vector to its starting address which is specified by the contents
of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a
known state during this type of reset as described in Section 5.
Resets.
2. STOP — The STOP instruction causes the oscillator to be turned
off and the processor to “sleep” until an external interrupt (IRQ) or
reset occurs.
3. WAIT — The WAIT instruction causes all processor clocks to stop,
but leaves the timer clock running. This “rest” state of the
processor can be cleared by reset, an external interrupt (IRQ), or
timer interrupt. There are no special wait vectors for these
individual interrupts.
4.4 Software Interrupt (SWI)
The SWI is an executable instruction and a nonmaskable interrupt. It is
executed regardless of the state of the I bit in the CCR. If the I bit is zero
(interrupts enabled), SWI executes after interrupts which were pending
when the SWI was fetched but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the
contents of memory locations $1FFC and $1FFD.
MC68HC705E5 — Rev. 1.0
General Release Specification
Interrupts
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