MC68HC705E5 Datasheet, PDF (42/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Resets
Freescale Semiconductor, Inc.
5.3 External Reset (RESET)
The RESET pin is the only external source of a reset. This pin is
connected to a Schmitt trigger input gate to provide an upper and lower
threshold voltage separated by a minimum amount of hysteresis. This
external reset occurs whenever the RESET pin is pulled below the lower
threshold and remains in reset until the RESET pin rises above the
upper threshold. This active-low input will generate the RST signal and
reset the CPU and peripherals. The only reset sources that can alter the
MCU’s operating mode are termination of the external reset input or the
internal computer operating properly (COP) watchdog reset.
NOTE: Activation of the RST signal is generally referred to as a reset of the
device, unless otherwise specified.
IRQ/V_TST
RESET
(PULSE WIDTH = 3xE-CLK)
OSC
DATA
ADDRESS
COP WATCHDOG
(COPR)
D
LATCH
R
CLOCKED
PH2
ONE-SHOT
V_DD
ADDRESS
STOPEN
POWER-ON RESET
(POR)
ILLEGAL ADDRESS
(ILLADDR)
DISABLED STOP
INSTRUCTION
S
D
LATCH
PH2
Figure 5-1. Reset Block Diagram
CPU
RST
TO IRQ
LOGIC
MODE
SELECT
TO OTHER
PERIPHERALS
General Release Specification
Resets
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MC68HC705E5 — Rev. 1.0