MC68HC705E5 Datasheet, PDF (36/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Interrupts
Freescale Semiconductor, Inc.
4.5 External Interrupt
If the I bit of the condition code reister (CCR) is set, all maskable
interrupts (internal and external) are disabled. Clearing the I bit enables
interrupts. The interrupt request is latched immediately following the
falling edge of IRQ. It is then synchronized internally and serviced by the
interrupt service routine located at the address specified by the contents
of $1FFA and $1FFB.
Either a level-sensitive and edge-sensitive trigger or an
edge-sensitive-only trigger is available as a mask option.
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I bit is cleared.
4.6 Timer Interrupt
Two different timer interrupt flags cause a timer interrupt whenever they
are set and enabled. The interrupt flags and enable bits are located in
the timer control and status register (TCSR). Either of these interrupts
will vector to the same interrupt service routine, located at the address
specified by the contents of memory location $1FF8 and $1FF9. For
additional information, refer to 8.3 Timer Control and Status Register.
General Release Specification
Interrupts
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MC68HC705E5 — Rev. 1.0