MC68HC705E5 Datasheet, PDF (68/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Computer Operating Properly (COP) Watchdog
10.3 System Control and Status Register
The SCSR is a read/write register containing the control flags for the
COP rate, COP inhibit, and IRQ level and status flags indicating the
cause of the last reset. Figure 10-1 shows the value of each bit in the
SCSR when coming out of reset.
Address: $0013
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
STOPR ILADR COPR CRS1 CRS0
Write:
Reset: 0
0
0
R
R
R
0
0
R = Determined by cause of previous reset
Figure 10-1. System Control and Status Register (SCSR)
NOTE: The debounce time for the IRQ input must be shorter than the COP
timeout period.
STOPR — Illegal STOP Instruction Reset
STOPR is a read-only status bit. This bit is set by the execution of a
STOP instruction when the STOP instruction option is disabled. This
bit is cleared by POR, external reset, or COP reset.
1 = Last reset was the execution of a disabled STOP instruction.
0 = Last reset was not the execution of a disabled STOP
instruction.
ILADR — Illegal Address Reset
ILADR is a read-only status bit. This bit is set by an ILADR reset, but
is cleared by POR, external reset, or COP reset.
1 = Last reset was an ILADR reset.
0 = Last reset was not an ILADR reset.
General Release Specification
Computer Operating Properly (COP) Watchdog
For More Information On This Product,
Go to: www.freescale.com
MC68HC705E5 — Rev. 1.0