MC68HC705E5 Datasheet, PDF (24/148 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Description
1.5.8 XFC
This pin provides a means for connecting an external filter capacitor to
the synthesizer PLL filter. For additional information concerning this
capacitor, see Section 9. Phase-Locked Loop (PLL) Synthesis.
1.5.9 V_DDSYN
NOTE:
This pin provides a separate power connection to the PLL synthesizer
which should be at the same potential as V_DD.
Any unused inputs and I/O ports should be tied to an appropriate logic
level (either V_DD or V_SS). Although the I/O ports of the MC68HC705E5
do not require termination, it is recommended to reduce the possibility of
static damage.
General Release Specification
General Description
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MC68HC705E5 — Rev. 1.0