MC68HC11E0CFNE3 Datasheet, PDF(88/242 Page) Freescale Semiconductor, Inc – M68HC11E Family

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MC68HC11E0CFNE3 Datasheet, PDF (88/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

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Resets and Interrupts

Table 5-4. Interrupt and Reset Vector Assignments

Vector Address

Interrupt Source

FFC0, C1 â FFD4, D5 Reserved

FFD6, D7

SCI serial system

â¢ SCI receive data register full

â¢ SCI receiver overrun

â¢ SCI transmit data register empty

â¢ SCI transmit complete

â¢ SCI idle line detect

FFD8, D9

SPI serial transfer complete

FFDA, DB

Pulse accumulator input edge

FFDC, DD

Pulse accumulator overflow

FFDE, DF

Timer overflow

FFE0, E1

Timer input capture 4/output compare 5

FFE2, E3

Timer output compare 4

FFE4, E5

Timer output compare 3

FFE6, E7

Timer output compare 2

FFE8, E9

Timer output compare 1

FFEA, EB

Timer input capture 3

FFEC, ED

Timer input capture 2

FFEE, EF

Timer input capture 1

FFF0, F1

Real-time interrupt

FFF2, F3

IRQ (external pin)

FFF4, F5

XIRQ pin

FFF6, F7

Software interrupt

FFF8, F9

Illegal opcode trap

FFFA, FB

COP failure

FFFC, FD

Clock monitor fail

FFFE, FF

RESET

CCR

Mask Bit

â

Local

Mask

â

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

X

None

None

None

None

None

RIE

RIE

TIE

TCIE

ILIE

SPIE

PAII

PAOVI

TOI

I4/O5I

OC4I

OC3I

OC2I

OC1I

IC3I

IC2I

IC1I

RTII

None

None

None

None

NOCOP

CME

None

5.5.1 Interrupt Recognition and Register Stacking

An interrupt can be recognized at any time after it is enabled by its local mask, if any, and by the global

mask bit in the CCR. Once an interrupt source is recognized, the CPU responds at the completion of the

instruction being executed. Interrupt latency varies according to the number of cycles required to

complete the current instruction. When the CPU begins to service an interrupt, the contents of the CPU

registers are pushed onto the stack in the order shown in Table 5-5. After the CCR value is stacked, the

I bit and the X bit, if XIRQ is pending, are set to inhibit further interrupts. The interrupt vector for the highest

priority pending source is fetched and execution continues at the address specified by the vector. At the

M68HC11E Family Data Sheet, Rev. 5.1

88

Freescale Semiconductor

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