MC68HC11E0CFNE3 Datasheet, PDF (24/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

General Description
NOTE
IRQ must be configured for level-sensitive operation if there is more than
one source of IRQ interrupt.
There should be a single pullup resistor near the MCU interrupt input pin (typically 4.7 kΩ). There must
also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low
until the MCU recognizes and acknowledges the interrupt request. If one or more interrupt sources are
still pending after the MCU services a request, the interrupt line will still be held low and the MCU will be
interrupted again as soon as the interrupt mask bit in the MCU is cleared (normally upon return from an
interrupt). Refer to Chapter 5 Resets and Interrupts.
V_PPE is the input for the 12-volt nominal programming voltage required for EPROM/OTPROM
programming. On devices without EPROM/OTPROM, this pin is only an XIRQ input.
CAUTION
During EPROM programming of the MC68HC711E9 device, the V_PPE pin
circuitry may latch-up and be damaged if the input current is not limited to
10 mA. For more information please refer to MC68HC711E9 8-Bit
Microcontroller Unit Mask Set Errata 3 (Freescale document order number
68HC711E9MSE3.
1.4.7 MODA and MODB (MODA/LIR and MODB/V_STBY)
During reset, MODA and MODB select one of the four operating modes:
• Single-chip mode
• Expanded mode
• Test mode
• Bootstrap mode
Refer to Chapter 2 Operating Modes and On-Chip Memory.
After the operating mode has been selected, the load instruction register (LIR) pin provides an open-drain
output to indicate that execution of an instruction has begun. A series of E-clock cycles occurs during
execution of each instruction. The LIR signal goes low during the first E-clock cycle of each instruction
(opcode fetch). This output is provided for assistance in program debugging.
The V_STBY pin is used to input random-access memory (RAM) standby power. When the voltage on this
pin is more than one MOS threshold (about 0.7 volts) above the V_DD voltage, the internal RAM and part
of the reset logic are powered from this signal rather than the V_DD input. This allows RAM contents to be
retained without V_DD power applied to the MCU. Reset must be driven low before V_DD is removed and
must remain low until V_DD has been restored to a valid level.
1.4.8 V_RL and V_RH
These two inputs provide the reference voltages for the analog-to-digital (A/D) converter circuitry:
• V_RL is the low reference, typically 0 Vdc.
• V_RH is the high reference.
For proper A/D converter operation:
• V_RH should be at least 3 Vdc greater than V_RL.
• V_RL and V_RH should be between V_SS and V_DD.
M68HC11E Family Data Sheet, Rev. 5.1
24
Freescale Semiconductor