MC68HC11E0CFNE3 Datasheet, PDF (123/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

SPI Registers
A write collision is normally a slave error because a slave has no control over when a master initiates a
transfer. A master knows when a transfer is in progress, so there is no reason for a master to generate a
write-collision error, although the SPI logic can detect write collisions in both master and slave devices.
The SPI configuration determines the characteristics of a transfer in progress. For a master, a transfer
begins when data is written to SPDR and ends when SPIF is set. For a slave with CPHA equal to 0, a
transfer starts when SS goes low and ends when SS returns high. In this case, SPIF is set at the middle
of the eighth SCK cycle when data is transferred from the shifter to the parallel data register, but the
transfer is still in progress until SS goes high. For a slave with CPHA equal to 1, transfer begins when the
SCK line goes to its active level, which is the edge at the beginning of the first SCK cycle. The transfer
ends in a slave in which CPHA equals 1 when SPIF is set.
8.7 SPI Registers
The three SPI registers are:
• Serial peripheral control register (SPCR)
• Serial peripheral status register (SPSR)
• Serial peripheral data register (SPDR)
These registers provide control, status, and data storage functions.
8.7.1 Serial Peripheral Control Register
Address: $1028
Bit 7
6
Read:
SPIE
SPE
Write:
Reset: 0
0
U = Unaffected
5
DWOM
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SPR1
U
Figure 8-3. Serial Peripheral Control Register (SPCR)
Bit 0
SPR0
U
SPIE — Serial Peripheral Interrupt Enable Bit
Set the SPE bit to 1 to request a hardware interrupt sequence each time the SPIF or MODF status flag
is set. SPI interrupts are inhibited if this bit is clear or if the I bit in the condition code register is 1.
0 = SPI system interrupts disabled
1 = SPI system interrupts enabled
SPE — Serial Peripheral System Enable Bit
When the SPE bit is set, the port D bit 2, 3, 4, and 5 pins are dedicated to the SPI function. If the SPI
is in the master mode and DDRD bit 5 is set, then the port D bit 5 pin becomes a general-purpose
output instead of the SS input.
0 = SPI system disabled
1 = SPI system enabled
DWOM — Port D Wired-OR Mode Bit
DWOM affects all port D pins.
0 = Normal CMOS outputs
1 = Open-drain outputs
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
123