MC68HC11E0CFNE3 Datasheet, PDF (107/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Receive Operation
7.4 Receive Operation
During receive operations, the transmit sequence is reversed. The serial shift register receives data and
transfers it to a parallel receive data register (SCDR) as a complete word. This double buffered operation
allows a character to be shifted in serially while another character is already in the SCDR. An advanced
data recovery scheme distinguishes valid data from noise in the serial data stream. The data input is
selectively sampled to detect receive data, and a majority voting circuit determines the value and integrity
of each bit. See Figure 7-2.
7.5 Wakeup Feature
The wakeup feature reduces SCI service overhead in multiple receiver systems. Software for each
receiver evaluates the first character of each message. The receiver is placed in wakeup mode by writing
a 1 to the RWU bit in the SCCR2 register. While RWU is 1, all of the receiver-related status flags (RDRF,
IDLE, OR, NF, and FE) are inhibited (cannot become set). Although RWU can be cleared by a software
write to SCCR2, to do so would be unusual. Normally, RWU is set by software and is cleared
automatically with hardware. Whenever a new message begins, logic alerts the sleeping receivers to
wake up and evaluate the initial character of the new message.
Two methods of wakeup are available:
• Idle-line wakeup
• Address-mark wakeup
During idle-line wakeup, a sleeping receiver awakens as soon as the RxD line becomes idle. In the
address-mark wakeup, logic 1 in the most significant bit (MSB) of a character wakes up all sleeping
receivers.
7.5.1 Idle-Line Wakeup
To use the receiver wakeup method, establish a software addressing scheme to allow the transmitting
devices to direct a message to individual receivers or to groups of receivers. This addressing scheme can
take any form as long as all transmitting and receiving devices are programmed to understand the same
scheme. Because the addressing information is usually the first frame(s) in a message, receivers that are
not part of the current task do not become burdened with the entire set of addressing frames. All receivers
are awake (RWU = 0) when each message begins. As soon as a receiver determines that the message
is not intended for it, software sets the RWU bit (RWU = 1), which inhibits further flag setting until the RxD
line goes idle at the end of the message. As soon as an idle line is detected by receiver logic, hardware
automatically clears the RWU bit so that the first frame of the next message can be received. This type
of receiver wakeup requires a minimum of one idle-line frame time between messages and no idle time
between frames in a message.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
107