MC68HC11E0CFNE3 Datasheet, PDF (156/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Electrical Characteristics
10.9 Control Timing
Characteristic^{(1) (2)}
1.0 MHz 2.0 MHz 3.0 MHz
Symbol
Unit
Min Max Min Max Min Max
Frequency of operation
E-clock period
f_o
t_CYC
dc 1.0 dc 2.0 dc 3.0
100
0
—
500
—
333
—
MHz
ns
Crystal frequency
f_XTAL
— 4.0 — 8.0 — 12.0 MHz
External oscillator frequency
Processor control setup time
t_PCSU = 1/4 t_CYC+ 50 ns
4 f_o
t_PCSU
dc 4.0 dc 8.0 dc 12.0 MHz
300 — 175 — 133 — ns
Reset input pulse width
To guarantee external reset vector
PW_RSTL 8
—
8
—
8
—
t_CYC
Minimum input time (can be pre-empted by internal reset)
1—1—1—
Mode programming setup time
t_MPS
2
—
2
—
2
—
t_CYC
Mode programming hold time
Interrupt pulse width, IRQ edge-sensitive mode
PW_IRQ = t_CYC + 20 ns
t_MPH
10 — 10 — 10 —
ns
PW_IRQ
102
0
—
520
—
353
—
ns
Wait recovery startup time
Timer pulse width input capture pulse accumulator input
PW_TIM = t_CYC + 20 ns
t_WRS
—4—4—
4
PW_TIM
102
0
—
520
—
353
—
t_CYC
ns
1. V_DD = 5.0 Vdc ±10%, V_SS = 0 Vdc, T_A = T_L to T_H, all timing is shown with respect to 20% V_DD and 70% V_DD, unless oth-
erwise noted
2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Chapter 5
Resets and Interrupts for further detail.
M68HC11E Family Data Sheet, Rev. 5.1
156
Freescale Semiconductor