MC68HC11E0CFNE3 Datasheet, PDF (62/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Analog-to-Digital (A/D) Converter
3.7 Multiple-Channel Operation
The two types of multiple-channel operation are:
1. When SCAN = 0, a selected group of four channels is converted one time each. The first result is
stored in A/D result register 1 (ADR1), and the fourth result is stored in ADR4. After the fourth
conversion is complete, all conversion activity is halted until a new conversion command is written
to the ADCTL register.
2. When SCAN = 1, conversions continue to be performed on the selected group of channels with the
fifth conversion being stored in register ADR1 (replacing the earlier conversion result for the first
channel in the group), the sixth conversion overwriting ADR2, and so on.
3.8 Operation in Stop and Wait Modes
If a conversion sequence is in progress when either the stop or wait mode is entered, the conversion of
the current channel is suspended. When the MCU resumes normal operation, that channel is resampled
and the conversion sequence is resumed. As the MCU exits wait mode, the A/D circuits are stable and
valid results can be obtained on the first conversion. However, in stop mode, all analog bias currents are
disabled and it is necessary to allow a stabilization period when leaving stop mode. If stop mode is exited
with a delay (DLY = 1), there is enough time for these circuits to stabilize before the first conversion. If
stop mode is exited with no delay (DLY bit in OPTION register = 0), allow 10 ms for the A/D circuitry to
stabilize to avoid invalid results.
3.9 A/D Control/Status Register
All bits in this register can be read or written, except bit 7, which is a read-only status indicator, and bit 6,
which always reads as 0. Write to ADCTL to initiate a conversion. To quit a conversion in progress, write
to this register and a new conversion sequence begins immediately.
Address: $1030
Bit 7
6
5
4
3
2
1
Bit 0
Read: CCF
Write:
SCAN MULT
CD
CC
CB
CA
Reset: 0
0
Indeterminate after reset
= Unimplemented
Figure 3-5. A/D Control/Status Register (ADCTL)
CCF — Conversion Complete Flag
A read-only status indicator, this bit is set when all four A/D result registers contain valid conversion
results. Each time the ADCTL register is overwritten, this bit is automatically cleared to 0 and a
conversion sequence is started. In the continuous mode, CCF is set at the end of the first conversion
sequence.
Bit 6 — Unimplemented
Always reads 0
SCAN — Continuous Scan Control Bit
M68HC11E Family Data Sheet, Rev. 5.1
62
Freescale Semiconductor