MC68HC11E0CFNE3 Datasheet, PDF (61/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Conversion Process
3.4 Conversion Process
The A/D conversion sequence begins one E-clock cycle after a write to the A/D control/status register,
ADCTL. The bits in ADCTL select the channel and the mode of conversion.
An input voltage equal to V_RL converts to $00 and an input voltage equal to V_RH converts to $FF (full
scale), with no overflow indication. For ratiometric conversions of this type, the source of each analog
input should use V_RH as the supply voltage and be referenced to V_RL.
3.5 Channel Assignments
The multiplexer allows the A/D converter to select one of 16 analog signals. Eight of these channels
correspond to port E input lines to the MCU, four of the channels are internal reference points or test
functions, and four channels are reserved. Refer to Table 3-1.
Table 3-1. Converter Channel Assignments
Channel
Number
1
2
3
4
5
6
7
8
9 – 12
13
14
15
16
Channel
Signal
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Reserved
V_RH(1)
V_RL(1)
(V_RH)/2⁽¹⁾
Reserved⁽¹⁾
1. Used for factory testing
Result in ADRx
if MULT = 1
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
—
ADR1
ADR2
ADR3
ADR4
3.6 Single-Channel Operation
The two types of single-channel operation are:
1. When SCAN = 0, the single selected channel is converted four consecutive times. The first result
is stored in A/D result register 1 (ADR1), and the fourth result is stored in ADR4. After the fourth
conversion is complete, all conversion activity is halted until a new conversion command is written
to the ADCTL register.
2. When SCAN = 1, conversions continue to be performed on the selected channel with the fifth
conversion being stored in register ADR1 (overwriting the first conversion result), the sixth
conversion overwriting ADR2, and so on.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
61