MC68HC11E0CFNE3 Datasheet, PDF (218/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Common Bootstrap Mode Problems
8491 '*
DECIMAL TO HEX CONVERSION
8492 '*
INPUT: K - INTEGER TO BE CONVERTED
8493 '*
OUTPUT: HX$ - TWO CHARACTER STRING WITH HEX CONVERSION
8494 '************************************************************************
8500 IF K > 255 THEN HX$="Too big":GOTO 8530
8510 HX$=MID$(H$,K\16+1,1)
'UPPER NIBBLE
8520 HX$=HX$+MID$(H$,(K MOD 16)+1,1) 'LOWER NIBBLE
8530 RETURN
9499 '******************** BOOT CODE ****************************************
9500 DATA 86, 23
'LDAA #$23
9510 DATA B7, 10, 02
'STAA OPT2 make port C wire or
9520 DATA 86, FE
'LDAA #$FE
9530 DATA B7, 10, 03
'STAA PORTC light 1 LED on port C bit 0
9540 DATA C6, FF
'LDAB #$FF
9550 DATA F7, 10, 07
'STAB DDRC make port C outputs
9560 DATA CE, 0F, A0
'LDX #4000 2msec at 2MHz
9570 DATA 18, CE, E0, 00
'LDY #$E000 Start of BUFFALO 3.4
9580 DATA 7E, BF, 00
'JMP $BF00 EPROM routine start address
9590 '***********************************************************************
Common Bootstrap Mode Problems
It is not unusual for a user to encounter problems with bootstrap mode because it is new to many users.
By knowing some of the common difficulties, the user can avoid them or at least recognize and quickly
correct them.
Reset Conditions vs. Conditions as Bootloaded Program Starts
It is common to confuse the reset state of systems and control bits with the state of these systems and
control bits when a bootloaded program in RAM starts.
Between these times, the bootloader program is executed, which changes the states of some systems
and control bits:
• The SCI system is initialized and turned on (Rx and Tx).
• The SCI system has control of the PD0 and PD1 pins.
• Port D outputs are configured for wire-OR operation.
• The stack pointer is initialized to the top of RAM.
• Time has passed (two or more SCI character times).
• Timer has advanced from its reset count value.
Users also forget that bootstrap mode is a special mode. Thus, privileged control bits are accessible, and
write protection for some registers is not in effect. The bootstrap ROM is in the memory map. The DISR
bit in the TEST1 control register is set, which disables resets from the COP and clock monitor systems.
Since bootstrap is a special mode, these conditions can be changed by software. The bus can even be
switched from single-chip mode to expanded mode to gain access to external memories and peripherals.
M68HC11 Bootstrap Mode, Rev. 1.1
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Freescale Semiconductor