MC68HC11E0CFNE3 Datasheet, PDF (105/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Chapter 7
Serial Communications Interface (SCI)
7.1 Introduction
The serial communications interface (SCI) is a universal asynchronous receiver transmitter (UART), one
of two independent serial input/output (I/O) subsystems in the M68HC11 E series of microcontrollers. It
has a standard non-return-to-zero (NRZ) format (one start bit , eight or nine data bits, and one stop bit).
Several baud rates are available. The SCI transmitter and receiver are independent, but use the same
data format and bit rate.
All members of the E series contain the same SCI, with one exception. The SCI system in the
MC68HC11E20 and MC68HC711E20 MCUs have an enhanced SCI baud rate generator. A divide-by-39
stage has been added that is enabled by an extra bit in the BAUD register. This increases the available
SCI baud rate selections. Refer to Figure 7-8 and 7.7.5 Baud Rate Register.
7.2 Data Format
The serial data format requires these conditions:
1. An idle line in the high state before transmission or reception of a message
2. A start bit, logic 0, transmitted or received, that indicates the start of each character
3. Data that is transmitted and received least significant bit (LSB) first
4. A stop bit, logic 1, used to indicate the end of a frame. A frame consists of a start bit, a character
of eight or nine data bits, and a stop bit.
5. A break, defined as the transmission or reception of a logic 0 for some multiple number of frames
Selection of the word length is controlled by the M bit of SCI control register (SCCR1).
7.3 Transmit Operation
The SCI transmitter includes a parallel transmit data register (SCDR) and a serial shift register. The
contents of the serial shift register can be written only through the SCDR. This double buffered operation
allows a character to be shifted out serially while another character is waiting in the SCDR to be
transferred into the
serial shift register. The output of the serial shift register is applied to TxD as long as transmission is in
progress or the transmit enable (TE) bit of serial communication control register 2 (SCCR2) is set. The
block diagram, Figure 7-1, shows the transmit serial shift register and the buffer logic at the top of the
figure.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
105