MC68HC11E0CFNE3 Datasheet, PDF (121/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

SPI Signals
SCK CYCLE #
SCK (CPOL = 0)
1
2
3
4
5
6
7
8
SCK (CPOL = 1)
SAMPLE INPUT
(CPHA = 0) DATA OUT
MSB
6
5
4
3
2
1
LSB
SAMPLE INPUT
(CPHA = 1) DATA OUT
MSB
6
5
4
3
2
1
SS (TO SLAVE)
1. SS ASSERTED
2. MASTER WRITES TO SPDR
3. FIRST SCK EDGE
4. SPIF SET
5. SS NEGATED
3
2
1
SLAVE CPHA = 1 TRANSFER IN PROGRESS
MASTER TRANSFER IN PROGRESS
SLAVE CPHA = 0 TRANSFER IN PROGRESS
Figure 8-2. SPI Transfer Format
LSB
4
5
8.5 SPI Signals
This subsection contains descriptions of the four SPI signals:
• Master in/slave out (MISO)
• Master out/slave in (MOSI)
• Serial clock (SCK)
• Slave select (SS)
Any SPI output line must have its corresponding data direction bit in DDRD register set. If the DDR bit is
clear, that line is disconnected from the SPI logic and becomes a general-purpose input. All SPI input lines
are forced to act as inputs regardless of the state of the corresponding DDR bits in DDRD register.
8.5.1 Master In/Slave Out
MISO is one of two unidirectional serial data signals. It is an input to a master device and an output from
a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device
is not selected.
8.5.2 Master Out/Slave In
The MOSI line is the second of the two unidirectional serial data signals. It is an output from a master
device and an input to a slave device. The master device places data on the MOSI line a half-cycle before
the clock edge that the slave device uses to latch the data.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
121