MC68HC11E0CFNE3 Datasheet, PDF (120/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Serial Peripheral Interface (SPI)
INTERNAL
MCU CLOCK
DIVIDER
÷2 ÷4 ÷16 ÷32
SELECT
SPI CONTROL
S
M
MSB
LSB
M
8--BIT SHIFT REGISTER
S
READ DATA BUFFER
CLOCK
CLOCK
S
LOGIC
M
MSTR
SPE
MISO
PD2
MOSI
PD3
SCK
PD4
SS
PD5
SPI STATUS REGISTER
SPI CONTROL REGISTER
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 8-1. SPI Block Diagram
8.4 Clock Phase and Polarity Controls
Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI
control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active
high or active low clock, and has no significant effect on the transfer format. The clock phase (CPHA)
control bit selects one of two different transfer formats. The clock phase and polarity should be identical
for the master SPI device and the communicating slave device. In some cases, the phase and polarity
are changed between transfers to allow a master device to communicate with peripheral slaves having
different requirements.
When CPHA equals 0, the SS line must be negated and reasserted between each successive serial byte.
Also, if the slave writes data to the SPI data register (SPDR) while SS is low, a write collision error results.
When CPHA equals 1, the SS line can remain low between successive transfers.
M68HC11E Family Data Sheet, Rev. 5.1
120
Freescale Semiconductor