MC68HC11E0CFNE3 Datasheet, PDF (22/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

General Description
1.4.2 RESET
A bidirectional control signal, RESET, acts as an input to initialize the MCU to a known startup state. It
also acts as an open-drain output to indicate that an internal failure has been detected in either the clock
monitor or computer operating properly (COP) watchdog circuit. The CPU distinguishes between internal
and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two E-clock
cycles after a reset has occurred. See Figure 1-7 and Figure 1-8.
CAUTION
Do not connect an external resistor capacitor (RC) power-up delay circuit
to the reset pin of M68HC11 devices because the circuit charge time
constant can cause the device to misinterpret the type of reset that
occurred.
Because the CPU is not able to fetch and execute instructions properly when V_DD falls below the minimum
operating voltage level, reset must be controlled. A low-voltage inhibit (LVI) circuit is required primarily for
protection of EEPROM contents. However, since the configuration register (CONFIG) value is read from
the EEPROM, protection is required even if the EEPROM array is not being used.
Presently, there are several economical ways to solve this problem. For example, two good external
components for LVI reset are:
1. The Seiko S0854HN (or other S805 series devices):
a. Extremely low power (2 µA)
a. TO-92 package
a. Limited temperature range, –20°C to +70°C
a. Available in various trip-point voltage ranges
2. The Freescale MC34064:
a. TO-92 or SO-8 package
a. Draws about 300 µA
a. Temperature range –40°C to 85°C
a. Well controlled trip point
a. Inexpensive
Refer to Chapter 5 Resets and Interrupts for further information.
1.4.3 Crystal Driver and External Clock Input (XTAL and EXTAL)
These two pins provide the interface for either a crystal or a CMOS- compatible clock to control the
internal clock generator circuitry. The frequency applied to these pins is four times higher than the desired
E-clock rate.
The XTAL pin must be left unterminated when an external CMOS- compatible clock input is connected to
the EXTAL pin. The XTAL output is normally intended to drive only a crystal. Refer to Figure 1-9 and
Figure 1-10.
CAUTION
In all cases, use caution around the oscillator pins. Load capacitances
shown in the oscillator circuit are specified by the crystal manufacturer and
should include all stray layout capacitances.
M68HC11E Family Data Sheet, Rev. 5.1
22
Freescale Semiconductor