MC68HC11E0CFNE3 Datasheet, PDF (142/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Timing Systems
9.5.2 Timer Interrupt Flag Register 2
Bits of this register indicate the occurrence of timer system events. Coupled with the four high-order bits
of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven
system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Address: $1025
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOF
Write:
RTIF PAOVF PAIF
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-22. Timer Interrupt Flag 2 Register (TFLG2)
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to 1 at the end of every RTI period. To clear RTIF, write a byte
to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 9.7 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 9.7 Pulse Accumulator.
Bits [3:0] — Unimplemented
Always read 0
9.5.3 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits control the pulse
accumulator and IC4/OC5 functions.
Address: $1026
Bit 7
6
5
4
3
2
1
Read:
Write:
Reset:
DDRA7
0
PAEN
0
PAMOD
0
PEDGE
0
DDRA3
0
I4/O5
0
RTR1
0
Figure 9-23. Pulse Accumulator Control Register (PACTL)
Bit 0
RTR0
0
DDRA7 — Data Direction for Port A Bit 7
Refer to Chapter 6 Parallel Input/Output (I/O) Ports.
PAEN — Pulse Accumulator System Enable Bit
Refer to 9.7 Pulse Accumulator.
PAMOD — Pulse Accumulator Mode Bit
Refer to 9.7 Pulse Accumulator.
M68HC11E Family Data Sheet, Rev. 5.1
142
Freescale Semiconductor