MC68HC11E0CFNE3 Datasheet, PDF (68/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Central Processor Unit (CPU)
4.2.5 Program Counter (PC)
The program counter, a 16-bit register, contains the address of the next instruction to be executed. After
reset, the program counter is initialized from one of six possible vectors, depending on operating mode
and the cause of reset. See Table 4-1.
Table 4-1. Reset Vector Comparison
Mode
Normal
Test or Boot
POR or RESET Pin
$FFFE, F
$BFFE, F
Clock Monitor
$FFFC, D
$BFFC, D
COP Watchdog
$FFFA, B
$BFFA, B
4.2.6 Condition Code Register (CCR)
This 8-bit register contains:
• Five condition code indicators (C, V, Z, N, and H),
• Two interrupt masking bits (IRQ and XIRQ)
• A stop disable bit (S)
In the M68HC11 CPU, condition codes are updated automatically by most instructions. For example, load
accumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or clear the N, Z,
and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange
instructions do not affect the condition codes. Refer to Table 4-2, which shows what condition codes are
affected by a particular instruction.
4.2.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an arithmetic operation.
The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate
with and through the carry bit to facilitate multiple-word shift operations.
4.2.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V bit is cleared.
4.2.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is 0. Otherwise, the Z
bit is cleared. Compare instructions do an internal implied subtraction and the condition codes, including
Z, reflect the results of that subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and
no other condition flags. For these operations, only = and ≠ conditions can be determined.
4.2.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (MSB = 1).
Otherwise, the N bit is cleared. A result is said to be negative if its most significant bit (MSB) is a 1. A quick
way to test whether the contents of a memory location has the MSB set is to load it into an accumulator
and then check the status of the N bit.
M68HC11E Family Data Sheet, Rev. 5.1
68
Freescale Semiconductor