MC68HC11E0CFNE3 Datasheet, PDF (162/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Electrical Characteristics
10.11 Peripheral Port Timing
Characteristic^{(1) (2)}
1.0 MHz
2.0 MHz
3.0 MHz
Symbol
Unit
Min Max Min Max Min Max
Frequency of operation
E-clock frequency
f_o
dc 1.0 dc 2.0 dc 3.0 MHz
E-clock period
t_CYC 1000 — 500 — 333 —
ns
Peripheral data setup time
MCU read of ports A, C, D, and E
t_PDSU 100 — 100 — 100 —
ns
Peripheral data hold time
MCU read of ports A, C, D, and E
t_PDH
50
—
50
—
50
—
ns
Delay time, peripheral data write
t_PWD = 1/4 t_CYC+ 100 ns
MCU writes to port A
MCU writes to ports B, C, and D
t_PWD
— 200 — 200 — 200
ns
— 350 — 225 — 183
Port C input data setup time
Port C input data hold time
Delay time, E fall to STRB
t_DEB = 1/4 t_CYC+ 100 ns
Setup time, STRA asserted to E fall⁽³⁾
t_IS
60
—
60
—
60
—
ns
t_IH
100 — 100 — 100 —
ns
t_DEB
— 350 — 225 — 183 ns
t_AES
0
—
0
—
0
—
ns
Delay time, STRA asserted to port C data output valid
t_PCD
— 100 — 100 — 100 ns
Hold time, STRA negated to port C data
3-state hold time
t_PCH
t_PCZ
10
—
10
—
10
—
ns
— 150 — 150 — 150 ns
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H, all timing is shown with respect to 20% V_DD and 70% V_DD, unless
otherwise noted
2. Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers, respec-
tively.)
3. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more cycle.
M68HC11E Family Data Sheet, Rev. 5.1
162
Freescale Semiconductor