MC68HC11E0CFNE3 Datasheet, PDF (135/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Output Compare
Register name: Timer Output Compare 3 Register (High) Address: $101A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset: 1
1
1
1
1
1
1
1
Register name: Timer Output Compare 3 Register (Low) Address: $101B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 9-10. Timer Output Compare 3 Register Pair (TOC3)
Register name: Timer Output Compare 4 Register (High) Address: $101C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset: 1
1
1
1
1
1
1
1
Register name: Timer Output Compare 4 Register (Low) Address: $101D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 9-11. Timer Output Compare 4 Register Pair (TOC4)
9.4.2 Timer Compare Force Register
The CFORC register allows forced early compares. FOC[1:5] correspond to the five output compares.
These bits are set for each output compare that is to be forced. The action taken as a result of a forced
compare is the same as if there were a match between the OCx register and the free-running counter,
except that the corresponding interrupt status flag bits are not set. The forced channels trigger their
programmed pin actions to occur at the next timer count transition after the write to CFORC.
The CFORC bits should not be used on an output compare function that is programmed to toggle its
output on a successful compare because a normal compare that occurs immediately before or after the
force can result in an undesirable operation.
Address: $100B
Bit 7
6
5
4
3
2
Read:
FOC1
Write:
FOC2
FOC3
FOC4
FOC5
1
Bit 0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-12. Timer Compare Force Register (CFORC)
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
135