MC68HC11E0CFNE3 Datasheet, PDF (145/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Pulse Accumulator
9.7.1 Pulse Accumulator Control Register
Four of this register’s bits control an 8-bit pulse accumulator system. Another bit enables either the OC5
function or the IC4 function, while two other bits select the rate for the real-time interrupt system.
Address: $1026
Bit 7
6
5
4
3
2
1
Read:
DDRA7
Write:
PAEN PAMOD PEDGE DDRA3
I4/O5
RTR1
Reset: 0
0
0
0
0
0
0
Figure 9-25. Pulse Accumulator Control Register (PACTL)
Bit 0
RTR0
0
DDRA7 — Data Direction for Port A Bit 7
Refer to Chapter 6 Parallel Input/Output (I/O) Ports.
PAEN — Pulse Accumulator System Enable Bit
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode Bit
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control Bit
This bit has different meanings depending on the state of the PAMOD bit, as shown in Table 9-7.
Table 9-7. Pulse Accumulator Edge Control
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Action on Clock
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A 0 on PAI inhibits counting.
A 1 on PAI inhibits counting.
DDRA3 — Data Direction for Port A Bit 3
Refer to Chapter 6 Parallel Input/Output (I/O) Ports.
I4/O5 — Input Capture 4/Output Compare 5 Bit
0 = Output compare 5 function enable (no IC4)
1 = Input capture 4 function enable (no OC5)
RTR[1:0] — RTI Interrupt Rate Select Bits
Refer to 9.5 Real-Time Interrupt (RTI).
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
145