MC68HC11E0CFNE3 Datasheet, PDF (171/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Serial Peripheral Interface Timing Characteristics
10.17 Serial Peripheral Interface Timing Characteristics
Num
Characteristic⁽¹⁾
Frequency of operation
E clock
E-clock period
Operating frequency
Master
Slave
Cycle time
1
Master
Slave
2
Enable lead time⁽²⁾
Slave
3
Enable lag time⁽²⁾
Slave
Symbol
f_o
t_CYC
f_op(m)
f_op(s)
t_CYC(m)
t_CYC(s)
t_lead(s)
t_lag(s)
E9
Min
Max
dc
3.0
333
—
f_o/32
f_o/2
dc
f_o
2
32
1
—
1
—
1
—
E20
Min
Max
dc
3.0
333
—
f_o/128
f_o/2
dc
f_o
2
128
1
—
1
—
1
—
Unit
MHz
ns
MHz
t_CYC
t_CYC
t_CYC
Clock (SCK) high time
4
Master
Slave
t_w(SCKH)m
t_w(SCKH)s
t_CYC–25
1/2
t_CYC–25
16 t_CYC
—
t_CYC–25
1/2
t_CYC–25
64 t_CYC
—
ns
Clock (SCK) low time
5
Master
Slave
t_w(SCKL)m
t_w(SCKL)s
t_CYC–25
1/2
t_CYC–25
16 t_CYC
—
t_CYC–25
1/2
t_CYC–25
64 t_CYC
—
ns
Data setup time (inputs)
6
Master
Slave
t_su(m)
30
—
30
—
ns
t_su(s)
30
—
30
—
Data hold time (inputs)
7
Master
Slave
Slave access time
8
CPHA = 0
CPHA = 1
t_h(m)
30
—
30
—
ns
t_h(s)
30
—
30
—
t_a
0
40
0
40
ns
0
40
0
40
Disable time (hold time
9
to high-impedance state)
Slave
t_dis
—
50
—
50
ns
10 _{Data valid}⁽³⁾ _{(after enable edge)}
t_v
—
50
—
50
ns
11
Data hold time (outputs)
(after enable edge)
t_ho
0
—
0
—
ns
1. V_DD = 5.0 Vdc ±10%, V_SS = 0 Vdc, T_A = T_L to T_H, all timing is shown with respect to 20% V_DD and 70% V_DD, unless other-
wise noted
2. Time to data active from high-impedance state
3. Assumes 200 pF load on SCK, MOSI, and MISO pins
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
171