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MC68HC11E0CFNE3 Datasheet, PDF (168/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family | |||
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Electrical Characteristics
10.15 Expansion Bus Timing Characteristics
Num
Characteristic(1)
1.0 MHz
2.0 MHz 3.0 MHz
Symbol
Unit
Min Max Min Max Min Max
Frequency of operation (E-clock frequency)
1 Cycle time
fo
tCYC
dc 1.0 dc 2.0 dc 3.0 MHz
1000 â 500 â 333 â ns
2 Pulse width, E low(2), PWEL = 1/2 tCYCâ23 ns
PWEL 477 â 227 â 146 â ns
3 Pulse width, E high(2), PWEH = 1/2 tCYCâ28 ns
4a E and AS rise time
PWEH 472 â 222 â 141 â ns
tr
â 20 â 20 â 20 ns
4b E and AS fall time
tf
â 20 â 20 â 15 ns
9 Address hold time(2) (3)a, tAH = 1/8 tCYCâ29.5 ns
tAH
95.5 â 33 â 26 â ns
Non-multiplexed address valid time to E rise
12
tAV = PWEL â(tASD + 80 ns)(2) (3)a
17 Read data setup time
tAV 281.5 â 94 â 54 â ns
tDSR
30 â 30 â 30 â ns
18 Read data hold time, max = tMAD
tDHR
0 145.5 0 83 0 51 ns
19 Write data delay time, tDDW = 1/8 tCYC+ 65.5 ns(2) (3)a
tDDW
â 190.5 â 128
71 ns
21 Write data hold time, tDHW = 1/8 tCYCâ29.5 ns(2) (3)a
tDHW 95.5 â 33 â 26 â ns
Multiplexed address valid time to E rise
22
tAVM = PWEL â(tASD + 90 ns)(2) (3)a
Multiplexed address valid time to AS fall
24
tASL = PWASH â70 ns(2)
tAVM 271.5 â 84 â 54 â ns
tASL
151 â 26 â 13 â ns
Multiplexed address hold time
25
tAHL = 1/8 tCYCâ29.5 ns(2) (3)b
26 Delay time, E to AS rise, tASD = 1/8 tCYCâ9.5 ns(2) (3)a
27 Pulse width, AS high, PWASH = 1/4 tCYCâ29 ns(2)
tAHL 95.5 â 33 â 31 â ns
tASD 115.5 â 53 â 31 â ns
PWASH 221 â 96 â 63 â ns
28 Delay time, AS to E rise, tASED = 1/8 tCYCâ9.5 ns(2) (3)b
tASED 115.5 â 53 â 31 â ns
29
MPU address access time(3)a
tACCA = tCYCâ(PWELâtAVM) âtDSRâtf
35 MPU access time, tACCE = PWEH âtDSR
tACCA 744.5 â 307 â 196 â ns
tACCE
â 442 â 192
111 ns
Multiplexed address delay (Previous cycle MPU read)
36
tMAD = tASD + 30 ns(2) (3)a
tMAD 145.5 â 83 â 51 â ns
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, all timing is shown with respect to 20% VDD and 70% VDD, unless oth-
erwise noted
2. Formula only for dc to 2 MHz
3. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 tCYCin the above formulas, where applicable:
(a) (1âdc) Ã 1/4 tCYC
(b) dc à 1/4 tCYC
Where:
dc is the decimal value of duty cycle percentage (high time)
M68HC11E Family Data Sheet, Rev. 5.1
168
Freescale Semiconductor
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