MC68HC11E0CFNE3 Datasheet, PDF (113/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

SCI Registers
FE — Framing Error Flag
FE is set when a 0 is detected where a stop bit was expected. Clear the FE flag by reading SCSR with
FE set and then reading SCDR.
0 = Stop bit detected
1 = Zero detected
Bit 0 — Unimplemented
Always reads 0
7.7.5 Baud Rate Register
Use this register to select different baud rates for the SCI system. The SCP[1:0] (SCP[2:0] in
MC68HC(7)11E20) bits function as a prescaler for the SCR[2:0] bits. Together, these five bits provide
multiple baud rate combinations for a given crystal frequency. Normally, this register is written once during
initialization. The prescaler is set to its fastest rate by default out of reset and can be changed at any time.
Refer to Table 7-1 for normal baud rate selections.
Address: $102B
Bit 7
6
Read:
TCLR
Write:
SCP2
Reset: 0
0
U = Unaffected
5
SCP1
0
4
SCP0
0
3
RCKB
0
2
SCR2
U
Figure 7-7. Baud Rate Register (BAUD)
1
SCR1
U
Bit 0
SCR0
U
TCLR — Clear Baud Rate Counter Bit (Test)
SCP[2:0] — SCI Baud Rate Prescaler Select Bits
NOTE
SCP2 applies to MC68HC(7)11E20 only. When SCP2 = 1, SCP[1:0] must
equal 0s. Any other values for SCP[1:0] are not decoded in the prescaler
and the results are unpredictable. Refer to Figure 7-8 and Figure 7-9.
RCKB — SCI Baud Rate Clock Check Bit (Test)
See Table 7-1.
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
113