MC68HC11E0CFNE3 Datasheet, PDF (136/242 Pages) Freescale Semiconductor, Inc – M68HC11E Family

Timing Systems
FOC[1:5] — Force Output Comparison Bit
When the FOC bit associated with an output compare circuit is set, the output compare circuit
immediately performs the action it is programmed to do when an output match occurs.
0 = Not affected
1 = Output x action occurs
Bits [2:0] — Unimplemented
Always read 0
9.4.3 Output Compare Mask Register
Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare. The bits
of the OC1M register correspond to PA[7:3].
Address: $100C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OC1M7
Write:
OC1M6
OC1M5
OC1M4
OC1M3
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-13. Output Compare 1 Mask Register (OC1M)
OC1M[7:3] — Output Compare Masks
0 = OC1 disabled
1 = OC1 enabled to control the corresponding pin of port A
Bits [2:0] — Unimplemented
Always read 0
9.4.4 Output Compare Data Register
Use this register with OC1 to specify the data that is to be stored on the affected pin of port A after a
successful OC1 compare. When a successful OC1 compare occurs, a data bit in OC1D is stored in the
corresponding bit of port A for each bit that is set in OC1M.
Address: $100D
Bit 7
6
5
4
3
2
Read:
OC1D7
Write:
OC1D6
OC1D5
OC1D4
OC1D3
1
Bit 0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-14. Output Compare 1 Data Register (OC1D)
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.
Bits [2:0] — Unimplemented
Always read 0
M68HC11E Family Data Sheet, Rev. 5.1
136
Freescale Semiconductor