K61P256M120SF3_1210 Datasheet, PDF (83/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

PTA0
PTA1
PTA3
PTA4
RESET_b
Table 58. Pins with active pull control after reset
Pin
Active pull direction after reset
pulldown
pullup
pullup
pullup
pullup
Pinout
8.2 K61 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
256 Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
E2 PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1 UART1_TX SDHC0_D1
I2C1_SDA RTC_CLKOUT
F2 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0
I2C1_SCL SPI1_SIN
F3 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK
UART1_CTS_b SDHC0_DCLK
G2 PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN UART1_RTS_b SDHC0_CMD
SPI1_SOUT
G7 VDD
VDD
VDD
H7 VDDINT
VDDINT
VDDINT
H8 VSS
VSS
VSS
F1 PTF17
DISABLED
PTF17
SPI2_SCK FTM0_CH4 UART0_RX
G1 PTF18
DISABLED
PTF18
SPI2_SOUT FTM1_CH0 UART0_TX
G3 PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3
G4 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
FTM3_CH0
H2 PTE6
DISABLED
PTE6
SPI1_PCS3 UART3_CTS_b I2S0_MCLK
FTM3_CH1
USB_SOF_
OUT
H1 PTF19
DISABLED
PTF19
SPI2_SIN FTM1_CH1 UART5_RX
H5 PTF20
DISABLED
PTF20
SPI2_PCS1 FTM2_CH0 UART5_TX
H3 PTE7
DISABLED
PTE7
UART3_RTS_b I2S0_RXD0
FTM3_CH2
H4 PTE8
ADC2_SE16 ADC2_SE16 PTE8
I2S0_RXD1 UART5_TX I2S0_RX_FS
FTM3_CH3
J1 PTE9
ADC2_SE17 ADC2_SE17 PTE9
I2S0_TXD1 UART5_RX I2S0_RX_BCLK
FTM3_CH4
J2 PTE10
DISABLED
PTE10
UART5_CTS_b I2S0_TXD0
FTM3_CH5
K1 PTE11
ADC3_SE16 ADC3_SE16 PTE11
UART5_RTS_b I2S0_TX_FS
FTM3_CH6
K3 PTE12
ADC3_SE17 ADC3_SE17 PTE12
I2S0_TX_BCLK
FTM3_CH7
G8 VDD
VDD
VDD
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
83