K61P256M120SF3_1210 Datasheet, PDF (53/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
6.6.1.2 16-bit ADC electrical characteristics
Table 30. 16-bit ADC characteristics (V_REFH = V_DDA, V_REFL = V_SSA)
Symbol Description
Conditions¹
Min.
Typ.²
Max.
Unit
I_{DDA_ADC} Supply current
0.215
—
ADC
• ADLPC = 1, ADHSC = 0 1.2
2.4
f_ADACK
asynchronous
clock source
• ADLPC = 1, ADHSC = 1 2.4
• ADLPC = 0, ADHSC = 0 3.0
4.0
5.2
• ADLPC = 0, ADHSC = 1 4.4
6.2
1.7
mA
3.9
MHz
6.1
MHz
7.3
MHz
9.5
MHz
Notes
3
t_ADACK = 1/
f_ADACK
Sample Time
See Reference Manual chapter for sample times
TUE
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
±4
±6.8
LSB⁴
5
—
±1.4
±2.1
DNL
Differential non-
linearity
INL Integral non-
linearity
E_FS Full-scale error
E_Q
Quantization
error
• 12-bit modes
• <12-bit modes
• 12-bit modes
• <12-bit modes
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
±0.7 -1.1 to +1.9 LSB⁴
5
-0.3 to 0.5
—
±0.2
—
±1.0 -2.7 to +1.9 LSB⁴
5
-0.7 to +0.5
—
±0.5
—
-4
-5.4
LSB⁴
V_ADIN =
—
-1.4
-1.8
V_DDA
5
—
-1 to 0
—
LSB⁴
—
—
±0.5
ENOB
Effective number 16-bit differential mode
of bits
• Avg = 32
• Avg = 4
6
12.8
14.5
—
bits
11.9
13.8
—
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
12.2
13.9
—
bits
11.4
13.1
—
bits
SINAD
Signal-to-noise
plus distortion
See ENOB
6.02 × ENOB + 1.76
dB
THD
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
—
–94
—
dB
16-bit single-ended mode
• Avg = 32
—
-85
—
dB
Table continues on the next page...
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
53