K61P256M120SF3_1210 Datasheet, PDF (67/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

RXCLK (input)
RXD[n:0]
RXDV
RXER
Peripheral operating requirements and behaviors
MII2
MII1
MII3
MII4
Valid data
Valid data
Valid data
Figure 30. MII receive signal timing diagram
6.8.1.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 41. RMII signal switching specifications
Num
—
RMII1
RMII2
RMII3
RMII4
RMII7
RMII8
Description
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
RMII_CLK pulse width low
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
RMII_CLK to TXD[1:0], TXEN invalid
RMII_CLK to TXD[1:0], TXEN valid
Min.
—
35%
35%
4
2
4
—
Max.
50
65%
65%
—
—
—
15
Unit
MHz
RMII_CLK
period
RMII_CLK
period
ns
ns
ns
ns
6.8.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
67