K61P256M120SF3_1210 Datasheet, PDF (71/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Num
DS9
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Peripheral operating requirements and behaviors
Table 46. Slave mode DSPI timing (limited voltage range)
Description
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Min.
2.7
4 x t_BUS
(t_SCK/2) − 2
—
0
2
7
—
—
Max.
3.6
15
—
(t_SCK/2) + 2
10
—
—
—
14
14
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
DS10
DS15
DS13
First data
DS14
First data
DS12
Data
Data
DS9
DS11
Last data
DS16
Last data
Figure 33. DSPI classic SPI timing — slave mode
6.8.8 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 47. Master mode DSPI timing (full voltage range)
Num
DS1
Description
Min.
Operating voltage
1.71
Frequency of operation
—
DSPI_SCK output cycle time
4 x t_BUS
Table continues on the next page...
Max.
3.6
15
—
Unit
V
MHz
ns
Notes
1
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
71