K61P256M120SF3_1210 Datasheet, PDF (74/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
Table 49. SDHC switching specifications over a limited operating voltage range (continued)
Num
SD6
SD7
SD8
Symbol Description
Min.
Max.
Unit
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_OD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_ISU
SDHC input setup time
t_IH
SDHC input hold time
5
—
ns
0
—
ns
Table 50. SDHC switching specifications over the full operating voltage
range
Num
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
Symbol
fpp
fpp
fpp
f_OD
t_WL
t_WH
t_TLH
t_THL
t_OD
t_ISU
t_IH
Description
Min.
Max.
Operating voltage
1.71
3.6
Card input clock
Clock frequency (low speed)
0
400
Clock frequency (SD\SDIO full speed)
0
25
Clock frequency (MMC full speed)
0
20
Clock frequency (identification mode)
0
400
Clock low time
7
—
Clock high time
7
—
Clock rise time
—
3
Clock fall time
—
3
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid)
-5
6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC input setup time
5
—
SDHC input hold time
1.3
—
Unit
V
kHz
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
SDHC_CLK
SD3
SD2
SD1
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 36. SDHC timing
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
74
Freescale Semiconductor, Inc.