K61P256M120SF3_1210 Datasheet, PDF (47/94 Pages) Freescale Semiconductor, Inc – K61 Sub-Family

Peripheral operating requirements and behaviors
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DDR_CLK
tDDRCK
tDDRCKH
tDDRCKL
DDR__CLK
DDR_CSn, DDR_WE
DDR_CAS, DDR_RAS
DDR_An
DDR_DQSn
DDR_DMn
tCMV
tCMH
CMD
ROW
CMD
COL
tDQSS
tQS
tQH
DDR_DQn
WD1 WD2 WD3 WD4
Figure 17. DDR write timing
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4
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DDR_CLK
DDR__CLK
DDR_CSn, DDR_WE
DDR_CAS, DDR_RAS
DDR_An
DDR_DQS (CL=2.5)
tDDRCK
tCMH
tCMV
CMD
ROW
tDDRCHH
CMD
COL
CL=2.5
DQS read preamble
tDDRCKL
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11
12
DDR_DQn (CL=2.5)
DDR_DQS (CL=3.0)
CL=3.0
RD1
DQS read preamble
RD2
RD3
RD4
DDR_DQn (CL=3.0)
RD1
RD2
RD3
RD4
Figure 18. DDR read timing
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
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